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a preliminary technical data sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc ? processor adsp-21365/adsp-21366 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel:781.329.4700 www.analog.com fax:781.326.8703 ? 2004 analog devices, inc. all rights reserved. summary high performance 32-bit/40-bit floating point processor optimized for high performance automotive audio processing audio decoder and post proce ssor-algorithm support with 32-bit floating-point implementations non-volatile memory may be configured to support audio decoders and post processor-algorithms like pcm, dolby digital ex, dolby prologic ii x, dts 96/24, neo:6, dts es, mpeg2 aac, mpeg2 2channel, mp3, and functions like bass management, delay, speaker equalization, graphic equalization, and more. decoder/post-processor algo- rithm combination support will vary depending upon the chip version and the system configurations. please visit www.analog.com/sharc single-instruction multiple -data (simd) computational architecture on-chip memory3m bit of on-chip sram and a dedicated 4m bit of on-chip mask-programmable rom code compatible with all othe r members of the sharc family the adsp-21365/6 is available with a 333 mhz core instruc- tion rate and unique audio centric peripherals such as the digital audio interface, s/pdif transceiver, dtcp (digital content transmission protocol) available on the adsp- 21365 only, serial ports, 8-channel asynchronous sample rate converter, precision clock generators and more. for complete ordering information, see ordering guide on page 51 figure 1. functional block diagram C processor core addr data iod addr data ioa addr data ioa sram 1m bit rom 2m bit sram 0.5m bit block 0 block 1 block 2 block 3 addr data ioa iop registers (memory mapped) see ?adsp-21365/6 memory and i/o interface features? section for details i/o processor and peripherals 6 jtag test & emulation 32 pm address bus dm address bus 32 pm data bus dm data bus 64 64 px register processing element (pey) processing element (pex) timer instruction cache 32 x 48-bit dag1 8x4x32 dag2 8x4x32 core processor program sequencer sram 1m bit rom 2m bit signal routing unit sram 0.5m bit 4 blocks of on-chip memory iod ioa iod iod spi sports idp pcg timers src spdif dtcp s
rev. pra | page 2 of 54 | september 2004 adsp-21365/6 preliminary technical data key features ? processor core at 333 mhz (3.0 ns) core instruction rate, the adsp-21365/6 performs 2 gflops/666 mmacs 3m bit on-chip sram (1m bit in blocks 0 and 1, and 0.50m bit in blocks 2 and 3) for simultaneous access by the core pro- cessor and dma 4m bit on-chip mask-programmable rom (2m bit in block 0 and 2m bit in block 1) dual data address generators (dags) with modulo and bit- reverse addressing zero-overhead looping with single-cycle loop setup, provid- ing efficient program sequencing single instruction multiple data (simd) architecture provides: two computational processing elements concurrent execution code compatibility with othe r sharc family members at the assembly level parallelism in busses and comp utational units allows sin- gle cycle execution (with or without simd) of a multiply operation, an alu operation, a dual memory read or write, and an instruction fetch transfers between memory and core at a sustained 5.4g bytes/s bandwidth at 333 mhz core instruction rate input/output features dma controller supports: 25 dma channels for transfers between adsp-21365/6 inter- nal memory and a variety of peripherals 32-bit dma transfers at core clock speed, in parallel with full- speed processor execution asynchronous parallel port provides access to asynchronous external memory 16 multiplexed address/data lines support 24-bit address external address range with 8-bit data or 16-bit address external address range with 16-bit data 55m byte per sec transfer rate external memory access in a dedicated dma channel 8- to 32-bit and 16- to 32-bit packing options programmable data cycle duration: 2 to 31 cclk digital audio interface (dai) includes six serial ports, two precision clock generators, an input data port, three tim- ers, an s/pdif transceiver, a dtcp cipher (adsp-21365 only), an 8-channel asynchro nous sample rate converter, an spi port, and a signal routing unit six dual data line serial ports that operate at up to 50m bits/s on each data line ? each has a clock, frame sync and two data lines that can be configur ed as either a receiver or transmitter pair left-justified sample pair and i 2 s support, programmable direction for up to 24 simultaneous receive or transmit channels using two i 2 s compatible stereo devices per serial port tdm support for telecommunications interfaces including 128 tdm channel support for newer telephony interfaces such as h.100/h.110 up to 12 tdm stream support, each with 128 channels per frame companding selection on a per channel basis in tdm mode input data port provides an additional input path to the pro- cessor core, configurable as eight channels of serial data or seven channels of serial data and a single channel of up to a 20-bit wide parallel data signal routing unit provides configurable and flexible con- nections between all dai compon ents?six serial ports, one spi port, eight channels of as ynchronous sample rate con- verters, an s/pdif receiver/transmitter, dtcp (digital content transmission protocol (adsp-21365 only), three timers, an spi port,10 interrupts, six flag inputs, six flag outputs, and 20 sru i/o pins (dai_px) two serial peripheral interfaces (spi): primary on dedicated pins, secondary on dai pins provide: master or slave serial boot through primary spi , full- duplex operation, master-slave mode multi-master sup- port, open drain outputs, programmable baud rates, clock polarities and phases 3 muxed flag/irq lines 1 muxed flag/timer expired line dedicated audio components s/pdif compatible digital audio receiver/transmitter sup- ports eiaj cp-340 (cp-1201), iec-958, aes/ebu standards left-justified, i 2 s or right-justified serial data input with 16, 18, 20 or 24-bit word widths (transmitter) two channel mode and single channel double frequency (scdf) mode digital transmission content protection (dtcp)?a crypto- graphic protocol for protecting audio content from unauthorized copying, in tercepting, and tampering (adsp-21365 only). sample rate converter (src) cont ains a serial input port, de- emphasis filter, sample rate converter (src) and serial output port providing up to -128db snr performance supports left justified, i 2 s, tdm and right justified 24, 20, 18 and 16-bit serial formats (input) pulse width modulation provides: 16 pwm outputs configured as four groups of four outputs supports center-aligned or edge-aligned pwm waveforms can generate complementary signals on two outputs in paired mode or independent signals in non-paired mode rom based security features include: jtag access to memory permitted with a 64-bit key protected memory regions that can be assigned to limit access under program cont rol to sensitive code pll has a wide variety of software and hardware multi- plier/divider ratios dual voltage: 3.3 v i/o, 1.2 v core available in 136-ball mini-bga and 144-lead lqfp packages (see ordering guide on page 51 )
adsp-21365/6 preliminary technical data rev. pra | page 3 of 54 | september 2004 general description the adsp-21365/6 sharc proce ssors are members of the simd sharc family of dsps th at feature analog devices' super harvard architecture. the adsp-21365/6 are source code compatible wi th the adsp-2126x, and adsp-2116x, dsps as well as with first generati on adsp-2106x sharc processors in sisd (single-instruction, single-data) mode. the adsp- 21365/6 are 32-bit/40-bit floating point processors optimized for high performance automotive audio applications with its large on-chip sram and mask-p rogrammable rom, multiple internal buses to eliminate i/o bottlenecks, and an innovative digital audio interface (dai). as shown in the functional block diagram on page 1 , the adsp-21365/6 uses two computatio nal units to deliver a signif- icant performance increase over the previous sharc processors on a range of signal processing algorithms. fabri- cated in a state-of-the-art, hi gh speed, cmos process, the adsp-21365/6 processor achieves an instruction cycle time of 3.0 ns at 333 mhz. with its si md computational hardware, the adsp-21365/6 can perform 2 gf lops running at 333 mhz. table 1 shows performance benchmarks for the adsp-21365/6. the adsp-21365/6 continues shar cs industry leading stan- dards of integration for dsps, combining a high performance 32-bit dsp core with integrated, on-chip system features. the block diagram of the adsp-21365/6 on page 1 , illustrates the following architectural features: two processing elements, each of which comprises an alu, multiplier, shifter and data register file data address generators (dag1, dag2) program sequencer with instruction cache pm and dm buses capable of supporting four 32-bit data transfers between me mory and the core at every core pro- cessor cycle three programmable interval timers with pwm genera- tion, pwm capture/pulse width measurement, and external event counter capabilities on-chip sram (3m bit) on-chip mask-programmable rom (4m bit) 8- or 16-bit parallel port that supports interfaces to off-chip memory peripherals jtag test access port the block diagram of the adsp-21365/6 on page 6 , illustrates the following architectural features: dma controller six full duplex serial ports two spi-compatible interface portsprimary on dedi- cated pins, secondary on dai pins digital audio interface that includes two precision clock generators (pcg), an input da ta port (idp), an s/pdif receiver/transmitter, eight ch annels asynchronous sample rate converters, dtcp cipher, si x serial ports, eight serial interfaces, a 20-bit parallel input port, 10 interrupts, six flag outputs, six flag inputs, three timers, and a flexible signal routing unit (sru) buses figure 2 on page 4 shows one sample conf iguration of a sport using the precision clock generators to interface with an i 2 s adc and an i 2 s dac with a much lower jitter clock than the serial port would generate it self. many other sru configura- tions are possible. adsp-21365/6 family core architecture the adsp-21365/6 is code compat ible at the assembly level with the adsp-2126x, adsp- 21160 and adsp-21161, and with the first generation adsp- 2106x sharc processors. the adsp-21365/6 shares architectura l features with the adsp- 2126x and adsp-2116x simd shar c processors, as detailed in the following sections. simd computational engine the adsp-/ contains two co mputational processing ele- ments that operate as a single-instruction multiple-data (simd) engine the processing elements are referred to as pe and pe and each contains an alu, multiplier, shifter and reg- ister file pe is always active, and pe may be enabled by setting the pee mode bit in the mode register when this mode is enabled, the same instruction is executed in both pro- cessing elements, but each processing element operates on different data this architecture is efficient at executing math intensive signal processing algorithms entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements when in simd mode, twice the data bandwidth is required to sustain computational operation in the pr ocessing elements because of this requirement, entering simd mode also doubles the band- width between memory and the processing elements when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file table 1. adsp-21365/6 benchmarks (at 333 mhz) benchmark algorithm speed (at 333 mhz) 1024 point complex fft (radix 4, with reversal) 27.9 s fir filter (per tap) 1 1 assumes two files in multichannel simd mode 1.5 ns iir filter (per biquad) 1 6.0 ns matrix multiply (pipelined) [3x3] [3x1] [4x4] [4x1] 13.5 ns 23.9 ns divide (y/) 10.5 ns inverse square root 16.3 ns
rev. pra | page 4 of 54 | september 2004 adsp-21365/6 preliminary technical data independent, paralle l computation units within each processing element is a set of computational units the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter these units perform all opera- tions in a single cycle the thre e units within each processing element are arranged in paralle l, maximiing computational throughput single multifunctio n instructions execute parallel alu and multiplier operations in simd mode, the parallel alu and multiplier operations occur in both processing ele- ments these computation unit s support ieee -bit single- precision floating-point, -bit extended precision floating- point, and -bit fixed-point data formats data register file a general-purpose data register file is contained in each pro- cessing element the register fi les transfer data between the computation units and the data buses, and store intermediate results these -port, -regist er ( primary, secondary) register files, comb ined with the adsp -x enhanced har- vard architecture, allow unco nstrained data flow between computation units and internal memory the registers in pe are referred to as r-r and in pe as s-s single-cycle fetch of instruction and four operands the adsp-/ features an en hanced harvard architecture in which the data memory (dm) bus transfers data and the pro- gram memory (pm) bus transfer s both instructions and data (see figure on page ) with the adsp-/s separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instructio n (from the cache), all in a sin- gle cycle instruction cache the adsp-/ includes an on -chip instructio n cache that enables three-bus operation for fe tching an instruction and four data values the cache is selectiveonly the instructions whose fetches conflict with pm bus data accesses are cached this cache allows full-speed executio n of core, looped operations such as digital filter multiply -accumulates, and fft butterfly processing data address generators with zero-overhead hardware circular buffer support the adsp-/s two data address genera tors (dags) are used for indirect addressing and implementing circular data buffers in hardware circular buffers allow efficient program- ming of delay lines and other data structures required in digital figure adsp-/ syst em sample configuration dai spi id p src spdif sp ort- sclk sda sfs sdb sru dai_p da i_ p da i_ p dai_p dai_p da i_ p dac (optioal) adc (optioal) fs clk sdat fs clk sdat clock flag- clki tal clk_cfg- bootcfg- addr parallel port ram, rom boo t r om i/o deice oe dt we rd wr out e d - 0 t reset t dsp-2 ddress dt o t r o s 0 p p s tiers
adsp-21365/6 preliminary technical data rev. pra | page 5 of 54 | september 2004 signal processing, and are commonly used in digital filters and fourier transforms. the two dags of the adsp-21365/6 con- tain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). the dags automatically handle address pointer wraparound, reduce over- head, increase performance, and simplify implementation. circular buffers can start and end at any memory location. flexible instruction set the -bit instruction word acco mmodates a variety of parallel operations, for concise programming for example, the adsp-/ can cond itionally execute a multiply, an add, and a subtract in both processi ng elements while branching and fetching up to four -bit valu es from memoryall in a single instruction adsp-/ memor ad i/o iterface features the adsp-/ adds the following architectural features to the simd sharc family core on-chip memory the adsp-/ contains three megabits of internal sram and four megabits of internal mask-programmable rom each block can be configured for different combinations of code and data storage (see table ) each memory block supports single- cycle, independent accesses by the core processor and i/o pro- cessor the adsp-/ me mory architecture, in combination with its separate on-chip buses, allow two data transfers from the core and one fr om the i/o processor, in a sin- gle cycle the adsp-/s, sram can be configured as a maximum of k words of -bit data, k words of -bit data, k words of -bit instructions (or - bit data), or combinations of different word sies up to three megabits all of the memory can be accessed as -bit, -bit, - bit, or -bit words a -bit floating-point storage format is supported that effectively dou- bles the amount of data that may be stored on-chip conversion between the -bit floating-point and -bit floating-point for- mats is performed in a single instruction while each memory block can store combinations of code and data, accesses are most efficient when one block st ores data using the dm bus for transfers, and the other block stor es instructions and data using the pm bus for transfers table 2. adsp-21365/6 internal memory space iop registers 0x0000 0000 - 0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 rom 0x0004 0000C0x0004 7fff block 0 rom 0x0008 0000C0x0008 aaaa block 0 rom 0x0008 0000C0x0008 ffff block 0 rom 0x0010 0000C0x0011 ffff reserved 0x0004 8000C0x0004 bfff reserved 0x0009 0000C0x0009 7fff reserved 0x0012 0000C0x0012 ffff block 0 ram 0x0004 c000C0x0004 ffff block 0 ram 0x0009 0000C0x0009 5555 block 0 ram 0x0009 8000C0x0009 ffff block 0 ram 0x0013 0000C0x0013 ffff block 1 rom 0x0005 0000C0x0005 7fff block 1 rom 0x000a 0000C0x000a aaaa block 1 rom 0x000a 0000C 0x000a ffff block 1 rom 0x0014 0000C0x0015 ffff reserved 0x0005 8000C0x0005 bfff reserved 0x000b 0000C 0x000b 7fff reserved 0x0016 0000C0x0016 ffff block 1 ram 0x0005 c000C0x0005 ffff block 1 ram 0x000b 0000C0x000b 5555 block 1 ram 0x000b 8000C0x000b ffff block 1 ram 0x0017 0000C0x0017 ffff block 2 ram 0x0006 0000C0x0006 1fff block 2 ram 0x000c 0000C0x000c 2aaa block 2 ram 0x000c 0000C0x000c 3fff block 2 ram 0x0018 0000C0x0018 7fff reserved 0x0006 2000C 0x0006 ffff reserved 0x000c 4000C 0x000d ffff reserved 0x0018 8000C0x001b ffff block 3 ram 0x0007 0000C0x0007 1fff block 3 ram 0x000e 0000C0x000e 2aaa block 3 ram 0x000e 0000C0x000e 3fff block 3 ram 0x001c 0000C0x001c 7fff reserved 0x0007 2000C 0x0007 ffff reserved 0x000e 4000C0x000f ffff reserved 0x001c 8000C0x001f ffff reserved 0x0020 0000C0xffff ffff
rev. pra | page 6 of 54 | september 2004 adsp-21365/6 preliminary technical data using the dm bus and pm buses, with one bus dedicated to each memory block, assures si ngle-cycle execution with two data transfers. in this case, the instruction must be available in the cache. dma controller the adsp-/s on-chip dm a controller allows data transfers without processor in tervention the dma controller operates independently and invi sibly to the processor core, allowing dma operations to o ccur while the core is simulta- neously executing its program in structions dma transfers can occur between the adsp-/ s internal memory and its serial ports, the spi-compatible (serial peripheral interface) ports, the idp (input data port ), the parallel data acquisition port (pdap) or the parallel port twenty-five channels of dma are available on the adsp-/ two for the spi interface, twelve via the serial ports, eight via the input data port, two for dtcp (or memory-to-memory data transfer when dtcp is not used), and one via the processors parallel port programs can be downloaded to the adsp-/ using dma transfers other dma features include interrupt ge neration upon completion of dma transfers, and dma chaini ng for automatic linked dma transfers digital audio interface (dai) the digital audio interface (dai ) provides the ability to con- nect various peripherals to any of the dsps dai pins (dai_p) programs make these connecti ons using the signal routing unit (sru, shown in figure ) the sru is a matrix routing unit (or group of multiplexers) that enables the peripherals provided by the dai to be intercon- nected under software control th is allows easy use of the dai associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with noncon- figurable signal paths the dai also includes six serial ports, an s/pdif receiver/trans- mitter, a dtcp cipher (adsp- only), a precision clock generator (pcg), eight channels of asynchronous sample rate converters, an input data port (idp), an spi port, six flag out- puts and six flag inputs, and th ree timers the idp provides an additional input path to the adsp-/ core, configurable as either eight channels of i s serial data or as seven channels plus a single -bit wide synchronous parallel data acquisition port each data channel has its own dma channel that is inde- pendent from the adsp -/s serial ports for complete information on using the dai, see the adsp- 2136x sharc processor hardware reference serial ports the adsp-/ features six sy nchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as analog devices adx family of audio codecs, adcs, and dacs the serial ports are made up of two data lines, a clock and frame sync the data lines can be programmed to either transmit or receive and each data line has a dedicated dma channel serial ports are enabled via programmable and simultaneous receive or transmit pins that support up to transmit or receive channels of audio data wh en all six sports are enabled, or six full duplex tdm streams of channels per frame the serial ports operate at a maximum data rate of m bits/s serial port data can be automatically transferred to and from on-chip memory via dedicated dma channels each of the serial ports can work in conunct ion with another serial port to provide tdm support one sport provides two transmit sig- nals while the other sport prov ides the two receive signals the frame sync and clock are shared serial ports operate in four modes standard dsp serial mode multichannel (tdm) mode i s mode left-ustified sa mple pair mode figure adsp-/ i/o processor and peripherals block diagram precisio clock geerators () spi port () serial ports () iput data ports () timers () dma cotroller iop registers (memor mapped) cotrol, status, data buffers parallel port gpio flags/ir/timep sigal routig uit address/data bus/ gpio control/gpio digital audio interface 25 channels to processor buses and system memory io address bus (18) src (8 channels) spdif (rx/tx) dtcp cipher pwm (16) io data bus (32) spi port (1) 4 20 i/o processor
adsp-21365/6 preliminary technical data rev. pra | page 7 of 54 | september 2004 left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitte d/receivedone sample on the high segment of the frame sync, the other on the low segment of the frame sync. programs have control over var- ious attributes of this mode. each of the serial ports supports the left-justified sample pair and i 2 s protocols (i 2 s is an industry st andard interface com- monly used by audio codecs, adcs and dacs such as the analog devices ad183x family), with two data pins, allowing four left-justified sample pair or i 2 s channels (using two stereo devices) per serial port, with a maximum of up to 24 i 2 s chan- nels. the serial ports permit little-endian or big-endian transmission formats an d word lengths selectab le from 3 bits to 32 bits. for the left-justified sample pair and i 2 s modes, data- word lengths are selectable between 8 bits and 32 bits. serial ports offer selectable synchron ization and transmit modes as well as optional parallel port the parallel port prov ides interfaces to sram and peripheral devices the multiplexed address and data pins (ad) can access -bit devices with up to bits of address, or -bit devices with up to bits of ad dress in either mode, - or - bit, the maximum data transfer rate is m bytes/sec dma transfers are used to move data to and from internal memory access to the core is also facilitated through the paral- lel port register read/write functions the rd , wr , and ale (address latch enable) pins are th e control pins for the parallel port serial peripheral (compatible) interface the adsp- sharc processor co ntains two serial periph- eral interface ports (spis) the spi is an industry standard synchronous serial link, enab ling the adsp-/ spi com- patible port to communicate with other spi compatible devices the spi consists of two data pins, one device select pin, and one clock pin it is a full-duplex sy nchronous serial interface, sup- porting both master and slave mo des the spi port can operate in a multimaster environment by interfacing with up to four other spi compatible devices, eith er acting as a master or slave device the adsp-/ spi co mpatible peripheral imple- mentation also features programmable baud rate and clock phase and polarities the adsp -/ spi compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention s/pdif compatible digital audio receiver/transmitter and synchronous/asynchronous sample rate converter the s/pdif transmitter has no separate dma channels it receives audio data in serial format and converts it into a biphase encoded signal the serial data input to the transmitter can be formatted as left ustified, i s or right ustified with word widths of , , , or bits the serial data, clock, and fram e sync inputs to the s/pdif transmitter are routed through th e signal routing unit (sru) they can come from a variety of sources such as the sports, external pins, the precision clock generators (pcgs), or the sample rate converters (src) and are controlled by the sru control registers the sample rate converter (src) contains four src blocks and is the same core as that us ed in the ad kh stereo asynchronous sample rate converter and provides up to db sr the src block is used to perform synchronous or asynchronous sample rate conver sion across independent stereo channels, without using internal processor resources the four src blocks can also be configur ed to operate together to con- vert multichannel audio data without phase mismatches finally, the src is used to clean up audio data from ittery clock sources such as the s/pdif receiver digital transmission content protection the dtcp specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying, intercepting and tampering as it traverses high performance digital buses, such as the ieee standard only legitimate entertainment content delivered to a source device via another approved copy protection syst em (such as the dd content scrambling system) will be protec ted by this copy protection system this feature is only available on the adsp- processor pulse width modulation the pwm module is a flexible , programmable, pwm waveform generator that can be programm ed to generate the required switching patterns for various appl ications related to motor and engine control or audio power control the pwm generator can generate either center-aligned or edge-aligned pwm wave- forms in addition, it can gene rate complementary signals on two outputs in paired mode or independent signals in non paired mode (applic able to a single group of four pwm waveforms) the entire pwm module has four groups of four pwm outputs each therefore, this module generates pwm outputs in total each pwm group produces two pairs of pwm signals on the four pwm outputs the pwm generator is capable of operating in two distinct modes while generating center-aligned pwm waveforms single update mode or double update mode in single update mode the duty cycle values are programmab le only once per pwm period this results in pwm patterns that are symmetrical about the mid-point of the pwm period in double update mode, a sec- ond updating of the pwm regist ers is implemented at the mid- point of the pwm period in this mode, it is possible to produce asymmetrical pwm patterns that produce lower harmonic dis- tortion in three-ph ase pwm inverters
rev. pra | page 8 of 54 | september 2004 adsp-21365/6 preliminary technical data timers the adsp-/ has a total of fo ur timers a core timer that can generate periodic software interrupts and three general pur- pose timers that can generate periodic interrupts and be independently set to operat e in one of three modes pulse waveform generation mode pulse width count /capture mode external event watchdog mode the core timer can be configur ed to use flag as a timer expired signal, and each general purpose timer has one bidirec- tional pin and four registers that implement its mode of operation a -bit configuration register, a -bit count register, a -bit period register, and a - bit pulse width register a sin- gle control and status register enables or disables all three general purpose timers independently rom based security the adsp-/ has a rom securi ty feature that provides hardware support for securing user software code by preventing unauthoried reading from the internal code when enabled when using this feature, the pr ocessor does not boot-load any external code, executing exclus ively from internal sram/rom additionally, the processor is no t freely accessible via the jtag port instead, a unique -bit ke y, which must be scanned in through the jtag or test access port will be assigned to each customer the device will ignore a wrong key emulation fea- tures and external boot modes are only available after the correct key is scanned program booting the internal memory of the adsp-/ boots at system power-up from an - bit eprom via the parallel port, an spi master, an spi slave or an internal boot booting is determined by the boot configuratio n (bootcfg) pins (see table on page ) selection of the boot source is controlled via the spi as either a master or slave device, or it can immediately begin exe- cuting from rom phase-locked loop the adsp-/ uses an on-chi p phase-locked loop (pll) to generate the internal clock for the core on power up, the clkcfg pins are used to select ratios of , , and (see table on page ) after booting, numerous other ratios can be selected vi a software control the ratios are made up of software configurable numerator val- ues from to and software config urable divisor values of , , , and power supplies the adsp-/ has separate po wer supply connections for the internal ( ddit ), external ( ddet ), and analog (a dd /a ss ) power supplies the inte rnal and analog supplies must meet the requirement the external supply must meet the requirement all external supply pins must be connected to the same power supply ote that the analog supply (a dd ) powers the adsp-/s clock generator pll to produce a stable clock, programs should provide an external circuit to filter the power input to the a dd pin place the filter as close as possible to the pin for an example circuit, see figure to prevent noise coupling, use a wide trace for the analog ground (a ss ) signal and install a decoupling capacitor as close as possible to the pin ote that the a ss and a dd pins specified in figure are inputs to the processor and not the analog ground plane on the board for more information, see electrical characteristics on page target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee jtag test acce ss port of the adsp-/ processor to monitor and contro l the target board processor during emulation analog devices dsp tools product line of jtag emulators provides emulation at full processor speed, allowing inspection and modifica tion of memory, registers, and processor stacks the processor s jtag interface ensures that the emulator will not affect target system loading or timing for complete information on analog devices sharc dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware users guide deelopmet tools the adsp-/ is supported with a complete set of crosscore software and hardware development tools, including analog devices emulators and isualdsp devel- opment environment the same emulator hardware that supports other sharc processors also fully emulates the adsp-/ the isualdsp proect manage ment environment lets pro- grammers develop and debug an application this environment includes an easy to use assemble r (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instru ction-level simulator, a c/c compiler, and a c/c runtime library that includes dsp and mathematical functions a key point for these tools is c/c code efficiency the compiler ha s been developed for efficient translation of c/c code to dsp assembly the sharc has architectural features that impr ove the efficiency of compiled c/c code the isualdsp debugger has a number of important fea- tures data visualiation is enha nced by a plotting package that offers a significant level of flexibility this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm as algorithms grow in com- plexity, this capability can have increasing significance on the figure analog power (a dd ) filter circuit ddit a dd a ss f 0.1 f 10
adsp-21365/6 preliminary technical data rev. pra | page 9 of 54 | september 2004 designers development schedule, increasing productivity. sta- tistical profiling enables the pr ogrammer to non intrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the software developer to passively gather important code executio n metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottlenecks in software quickly and effi- ciently. by using the profiler , the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: view mixed c/c++ and assembly code (interleaved source and object information) insert breakpoints set conditional breakpoints on registers, memory, and stacks trace instruction execution perform linear or statistical profiling of program execution fill, dump, and graphically plot the contents of memory perform source level debugging create custom debugger windows the visualdsp++ idde lets programmers define and manage dsp software development. its di alog boxes and property pages let programmers configure and ma nage all of the sharc devel- opment tools, including the color syntax highlighting in the visualdsp++ editor. this capabi lity permits programmers to: control how the development tools process inputs and generate outputs maintain a one-to-one correspondence with the tools command line switches the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. the vdk features include threads, critical and unscheduled regions, semaphores, events, and device flags. the vd k also supports priority-based, preemptive, cooperative, and time-sliced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a spec ific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but ca n also be used via standard command line tools. when the vdk is used, the development environment assists the develope r with many error-prone tasks and assists in managing system resources, automating the gen- eration of various vdk based objects, and visualizing the system state, when debugging an application that uses the vdk. visualdsp++ component softwa re engineering (vcse) is analog devices technology fo r creating, using, and reusing software components (independent modules of substantial functionality) to quickly and reli ably assemble so ftware applica- tions. download components from the web and drop them into the application. publish component archives from within visualdsp++. vcse supports co mponent implementation in c/c++ or assembly language. use the expert linker to visually manipulate the placement of code and data on the embedded system. view memory utiliza- tion in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with the drag of the mouse, examine run time stack and heap usage. the expert linker is fully compatible with the existing linker defi- nition file (ldf), allowing th e developer to move between the graphical and textual environments. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hard- ware tools include sharc processor pc plug-in cards. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test an d debug hardware and software systems analog devices has supplied an ieee jtag test access port (tap) on each jtag dsp onintrusive in- circuit emulation is a ssured by the use of the processors jtag interfacethe emulator does not a ffect target syst em loading or timing the emulator uses the tap to access the internal fea- tures of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers the processor must be halted to send data and com- mands, but once an operatio n has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing to use these emulators, the target board must include a header that connects the dsps jtag port to the emulator for details on target board desi gn issues including mechanical layout, single processor conne ctions, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the ee-68: analog devices jt ag emulation technical reference on the analog devices wesite wwwanalogcom use site search on ee-68 this document is udated regularl to ee ace with imrovements to emulator suort evaluation kit analog devices offers a range of ez-kit lite evaluation plat- forms to use as a cost effective method to learn more about developing or prototyping appl ications with analog devices processors, platforms, and softwa re tools each ez-kit lite includes an evaluation board along with an evaluation suite of the isualdsp development and debugging environment with the c/c compiler, assemble r, and linker also included
rev. pra | page 10 of 54 | september 2004 adsp-21365/6 preliminary technical data are sample application progra ms, power supply, and a usb cable. all evaluation versions of the software tools are limited for use only with the ez-kit lite product. the usb controller on the ez-k it lite board connects the board to the usb port of th e user?s pc, enabling the visualdsp++ evaluation suite to emulate the on-board proces- sor in-circuit. this permits the customer to download, execute, and debug programs for the ez-kit lite system. it also allows in-circuit programming of the on-board flash device to store user-specific boot code, enabling the board to run as a standal- one unit without being connected to the pc. with a full version of visualdsp ++ installed (sold separately), engineers can develop software fo r the ez-kit lite or any cus- tom defined system. connecting one of analog devices jtag emulators to the ez-kit lite board enables high-speed, non- intrusive emulation. additional information this data sheet provides a general overview of the adsp- 21365/6 architecture and function ality. for detailed informa- tion on the adsp-2136x family core architecture and instruction set, refer to the adsp-2136x sharc processor hardware reference and the adsp-2136x sharc processor programming reference
adsp-21365/6 preliminary technical data rev. pra | page 11 of 54 | september 2004 pin function descriptions adsp-21365/6 pin definitions are li sted below. inputs identified as synchronous (s) must meet ti ming requirements with respect to clkin (or with respect to tck for tms and tdi). inputs identified as asynchro nous (a) can be asserted asynchronously to clkin (or to tck for trst ). tie or pull unused inputs to v ddext or gnd, except for the following: dai_px, spiclk, miso, mosi, emu , tms, trst , tdi, and ad15C0 (note: these pins have pullup resistors.) the following symbol s appear in the type column of table 3 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open drain, and t = three-state , (pd) = pulldown resistor, (pu) = pullup resistor. table 3. pin descriptions pin type state during and after reset function ad15C0 i/o/t (pu) three-state with pullup enabled parallel port address/data. the adsp-21365/6 parallel port and its corresponding dma unit output addresses and data for peripherals on these multiplexed pins. the multiplex state is determined by the ale pin. the parallel port can operate in either 8-bit or 16-bit mode. each ad pin has a 22.5 k ? internal pullup resistor. see address data modes on page 14 for details of the ad pin operation. for 8-bit mode: ale is automatically asserted whenever a change occurs in the upper 16 external address bits, a23C8; ale is used in conjunction with an external latch to retain the values of the a23C8. for 16-bit mode: ale is automatically asserted whenever a change occurs in the address bits, a15C0; ale is used in conjunct ion with an external latch to retain the values of the a15C0. to use these pins as flags (flags15C0) or pwms (pwm15C0), 1) set (=1) bit 20 of the sysctl register to disable the parallel port, 2) set (=1) bits 22C25 of the sysctl register to enable flags in groups of four (bit 22 for flags3C0, bit 23 for flags7C4 etc.) or, set (=1) bits 26C29 of the sysctl register to enable pwms in groups of four (bit 26 for pwm0C3, bit 27 for pwm4C7, and so on). when used as an input, the idp channel 0 can use th ese pins for parallel input data. rd o (pu) three-state, driven high 1 parallel port read enable. rd is asserted low whenever the processor reads 8-bit or 16-bit data from an external memory device. when ad15C0 are flags, this pin remains deasserted. rd has a 22.5 k ? internal pullup resistor. wr o (pu) three-state, driven high 1 parallel port write enable. wr is asserted low whenever the processor writes 8-bit or 16-bit data to an external memory device. when ad15C0 are flags, this pin remains deasserted. wr has a 22.5 k ? internal pullup resistor. ale o (pd) three-state, driven low 1 parallel port address latch enable. ale is asserted whenever the processor drives a new address on the parallel port address pins . on reset, ale is active high. however, it can be reconfigured using software to be active low. when ad15C0 are flags, this pin remains deasserted. ale has a 20 k ? internal pulldown resistor. flag3C0 i/o/a three-state flag pins. each flag pin is configured via control bits as either an input or output. as an input, it can be tested as a condition. as an output, it can be used to signal external peripherals. these pins can be used as an spi interface slave select output during spi mastering. these pins are also multiplexed with the irqx and the timexp signals. in spi master boot mode, flag0 is the slave select pin that must be connected to an spi eprom. flag0 is configured as a slave se lect during spi master boot. when bit 16 is set (=1) in the sysctl register, flag0 is configured as irq0 . when bit 17 is set (=1) in the sysctl register, flag1 is configured as irq1 . when bit 18 is set (=1) in the sysctl register, flag2 is configured as irq2 . when bit 19 is set (=1) in the sysctl register, flag3 is configured as timexp which indicates that the system timer has expired.
rev. pra | page 12 of 54 | september 2004 adsp-21365/6 preliminary technical data dai_p20C1 i/o/t (pu) three-state with programmable pullup digital audio interface pins . these pins provide the physical interface to the sru. the sru configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to th e pins output enable. the configuration registers of these peripherals then determines the exact behavior of the pin. any input or output signal present in the sru may be routed to any of these pins. the sru provides the connection from the serial ports, input data port, precision clock gener- ators and timers, sample rate converters and spi to the dai_p20C1 pins these pins have internal 22.5 k ? pullup resistors which are enable d on reset. these pullups can be disabled in the dai_pin_pullup register. spiclk i/o (pu) three-state with pullup enabled serial peripheral interface clock signal . driven by the master, this signal controls the rate at which data is transferred. the master may transmit data at a variety of baud rates. spiclk cycles once for each bit transmi tted. spiclk is a gated clock that is active during data transfers, only for the length of the transferred word. slave devices ignore the serial clock if the slave select input is driv en inactive (high). spiclk is used to shift out and shift in the data driven on the miso and mosi lines. the data is always shifted out on one clock edge and sampled on the opposite edge of the clock. clock polarity and clock phase relative to data are progra mmable into the spic tl control register and define the transfer format. spiclk has a 22.5 k ? internal pullup resistor. spids i input only serial peripheral interface slave device select . an active low signal used to select the processor as an spi slave device. this input signal behaves like a chip select, and is provided by the master device for the slave devices. in multimaster mode the dsps spids signal can be driven by a slave device to signal to the processor (as spi master) that an error has occurred, as some other devi ce is also trying to be the master device. if asserted low when the device is in master mode, it is considered a multimaster error. for a single-master, multiple-slave configur ation where flag pins are used, this pin must be tied or pulled high to v ddext on the master device. for adsp-21365/6 to adsp-21365/6 spi interaction, any of the master adsp-21365/6's flag pins can be used to drive the spids signal on the adsp-21365/6 spi slave device. mosi i/o (o/d) (pu) three-state with pullup enabled spi master out slave in . if the adsp-21365/6 is configured as a master, the mosi pin becomes a data transmit (output) pin, transmitting output data. if the adsp-21365/6 is configured as a slave, the mosi pin becomes a data receive (input) pin, receiving input data. in an adsp-21365/6 spi interconne ction, the data is shifted out from the mosi output pin of the master and shifted into the mosi input(s) of the slave(s). mosi has a 22.5 k ? internal pullup resistor. miso i/o (o/d) (pu) three-state with pullup enabled spi master in slave out . if the adsp-21365/6 is configured as a master, the miso pin becomes a data receive (input) pin, receiv ing input data. if the adsp-21365/6 is configured as a slave, the miso pin becomes a data transmit (output) pin, transmitting output data. in an adsp-21365/6 spi interco nnection, the data is shifted out from the miso output pin of the slave and shifted into the miso input pin of the master. miso has a 22.5 k ? internal pullup resistor. miso can be configured as o/d by setting the opd bit in the spictl register. note: only one slave is allowed to transmit data at any given time. to enable broadcast transmission to multiple spi-slaves, the processor's miso pin may be disabled by setting (=1) bit 5 (dmiso) of the spictl register. bootcfg1C0 i input only boot configuration select . this pin is used to select the boot mode for the processor. the bootcfg pins must be valid before reset is asserted. see table 6 for a description of the boot modes. table 3. pin descriptions (continued) pin type state during and after reset function
adsp-21365/6 preliminary technical data rev. pra | page 13 of 54 | september 2004 clkin i input only local clock in . used in conjunction with xtal. clkin is the adsp-21365/6 clock input. it configures the adsp-21365/6 to use either its internal clock generator or an external clock source. connecting the necessary components to clkin and xtal enables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the adsp-21365/6 to use the external clock source such as an external clock oscillator. the core is clocked either by the pll output or this clock input depending on the clkcfg1C0 pin sett ings. clkin may not be halted, changed, or operated below the specified frequency. xtal o output only 2 crystal oscillator terminal . used in conjunction with clkin to drive an external crystal. clkcfg1C0 i input only core/clkin ratio control . these pins set the start up clock frequency. see table 7 for a description of the clock configuration modes. note that the operating frequency can be changed by programming the pll multiplier and divider in the pmctl register at any time after the core comes out of reset. rstout /clkout o output only local clock out/ reset out . drives out the core reset signal to an external device. clkout can also be configured as a reset out pin.the functionality can be switched between the pll output clock and reset out by setting bit 12 of the pmctreg register. the default is reset out. reset i/a input only processor reset . resets the adsp-21365/6 to a know n state. upon deassertion, there is a 4096 clkin cycle latency for the pll to lock. after this time, the core begins program execution from the hardware reset vector address. the reset input must be asserted (low) at power-up. tck i input only 3 test clock (jtag) . provides a clock for jtag boundary scan. tck must be asserted (pulsed low) after power-up or held low for proper operation of the adsp-21365/6. tms i/s (pu) three-state with pullup enabled test mode select (jtag) . used to control the test state machine. tms has a 22.5 k ? internal pullup resistor. tdi i/s (pu) three-state with pullup enabled test data input (jtag) . provides serial data for the boundary scan logic. tdi has a 22.5 k ? internal pullup resistor. tdo o three-state 4 test data output (jtag) . serial scan output of the boundary scan path. trst i/a (pu) three-state with pullup enabled test reset (jtag) . resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the adsp-21365/6. trst has a 22.5 k ? internal pullup resistor. emu o (o/d) (pu) three-state with pullup enabled emulation status . must be connected to the adsp-21365/6 analog devices dsp tools product line of jtag emulators target board connector only. emu has a 22.5 k ? internal pullup resistor. v ddint p core power supply . nominally +1.2 v dc and supplies the processors core (13 pins on the mini-bga package, 32 pins on the lqfp package). v ddext p i/o power supply . nominally +3.3 v dc. (6 pins on the mini-bga package, 10 pins on the lqfp package). a vdd p analog power supply . nominally +1.2 v dc and supplies the processors internal pll (clock generator). this pin has the same specifications as v ddint , except that added filtering circuitry is required. for more information, see power supplies on page 8. a vss g analog power supply return . gnd g power supply return . (54 pins on the mini-bga package, 39 pins on the lqfp package). 1 rd , wr , and ale are three-stated (and not driven) only when reset is active. 2 output only is a three-state driver wi th its output path always enabled. 3 input only is a three-state driver with both output path and pullup disabled. 4 three-state is a three-state driver with pullup disabled. table 3. pin descriptions (continued) pin type state during and after reset function
rev. pra | page 14 of 54 | september 2004 adsp-21365/6 preliminary technical data address data pins as flags to use these pins as flags (fla gs15?0) set (=1) bit 20 of the sysctl register to disable the pa rallel port. then set (=1) bits 22 to 25 in the sysctl register accordingly. address data modes the following table shows the func tionality of the ad pins for 8-bit and 16-bit transfers to the parallel port. for 8-bit data transfers, ale latches address bi ts a23?a8 when asserted, fol- lowed by address bits a7?a0 and data bits d7?d0 when deasserted. for 16-bit data transf ers, ale latches address bits a15?a0 when asserted, followed by data bits d15?d0 when deasserted. boot modes core instruction rate to clkin ratio modes for details on processor timing, see timing specifications and figure 5 on page 17 . table 4. ad15C0 to flag pin mapping ad pin flag pin ad pin flag pin ad0 flag8 ad8 flag0 ad1 flag9 ad9 flag1 ad2 flag10 ad10 flag2 ad3 flag11 ad11 flag3 ad4 flag12 ad12 flag4 ad5 flag13 ad13 flag5 ad6 flag14 ad14 flag6 ad7 flag15 ad15 flag7 table 5. address/ data mode selection ep data mode ale ad7C0 function ad15C8 function 8-bit asserted a15C8 a23C16 8-bit deasserted d7C0 a7C0 16-bit asserted a7C0 a15C8 16-bit deasserted d7C0 d15C8 table 6. boot mode selection bootcfg1C0 booting mode 00 spi slave boot 01 spi master boot 10 parallel port boot via eprom table 7. core instruction rate/ clkin ratio selection clkcfg1C0 core to clkin ratio 00 6:1 01 32:1 10 16:1
adsp-21365/6 preliminary technical data rev. pra | page 15 of 54 | september 2004 adsp-21365/6 specifications recommended operating conditions electrical characteristics parameter 1 1 specifications subject to change without notice. k grade b grade c grade min max min max min max unit v ddint internal (core) supply voltage 1.14 1.26 1.14 1.26 0.95 1.05 v a vdd analog (pll) supply voltag e 1.14 1.26 1.14 1.26 0.95 1.05 v v ddext external (i/o) supply voltage 3.13 3.47 3.13 3.47 3.13 3.47 v v ih 2 2 applies to input and bid irectional pins: ad15C0, flag3C0, dai_px, spiclk, mosi, miso, spids , bootcfgx, clkcfgx, reset , tck, tms, tdi, trst . high level input voltage @ v ddext = max 2.0 v ddext + 0.5 2.0 v ddext + 0.5 2.0 v ddext + 0.5 v v il 2 low level input voltage @ v ddext = min C0.5 +0.8 C0.5 +0.8 C0.5 +0.8 v v ih_clkin 3 3 applies to input pin clkin. high level input voltage @ v ddext = max 1.74 v ddext + 0.5 1.74 v ddext + 0.5 1.74 v ddext + 0.5 v v il_clkin low level input voltage @ v ddext = min C0.5 +1.19 C0.5 +1.19 C0.5 +1.19 v t amb 4, 5 4 see thermal characteristics on page 44 for information on thermal specifications. 5 see engineer-to-engineer note (no. tbd) for further information. ambient operating temperature 0 +70 C40 +85 C40 +105 c parameter 1 test conditions min max unit v oh 2 high level output voltage @ v ddext = min, i oh = C1.0 ma 3 2.4 v v ol 2 low level output voltage @ v ddext = min, i ol = 1.0 ma 3 0.4 v i ih 4, 5 high level input current @ v ddext = max, v in = v ddext max 10 a i il 4 low level input current @ v ddext = max, v in = 0 v 10 a i ilpu 5 low level input current pullup @ v ddext = max, v in = 0 v 200 a i ozh 6, 7 three-state leakage current @ v ddext = max, v in = v ddext max 10 a i ozl 6 three-state leakage current @ v ddext = max, v in = 0 v 10 a i ozlpu 7 three-state leakage current pullup @ v ddext = max, v in = 0 v 200 a i dd-intyp 8, 9 supply current (internal) t cclk = min, v ddint = nom 500 ma ai dd 10 supply current (analog) a vdd = max 10 ma c in 11, 12 input capacitance f in =1 mhz, t case =25c, v in =1.2v 4.7 pf 1 specifications subject to change without notice. 2 applies to output and bidir ectional pins: ad15C0, rd , wr , ale, flag3C0, dai_px, spiclk, mosi, miso, emu , tdo, clkout, xtal. 3 see output drive currents on page 43 for typical drive current capabilities. 4 applies to input pins: spids , bootcfgx, clkcfgx, tck, reset , clkin. 5 applies to input pins with 22.5 k ? ?
rev. pra | page 16 of 54 | september 2004 adsp-21365/6 preliminary technical data maximum power dissipation the data in this table is based on theta ja ( 70 c 3.33w 2.10w 2.44w 2.18w 85 c 2.42w n/a 1.77w n/a 105 c1.21wn/an/an/a parameter rating internal (core) supply voltage (v ddint ) 1 1 stresses greater than those listed above may cause permanent da mage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in th e operational sections of this specification is not implied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. C0.3 v to +1.5 v analog (pll) supply voltage (a vdd ) 1 C0.3 v to +1.5 v external (i/o) supply voltage (v ddext ) 1 C0.3 v to +4.6 v input voltageC0.5 v to v ddext 1 + 0.5 v output voltage swingC0.5 v to v ddext 1 + 0.5 v load capacitance 1 200 pf storage temperature range 1 C65 c to +150 c junction temperature under bias 125 c caution esd (electrostatic discharge) se nsitive device. electrostatic charges as high as 4000v readily accumulate on the human body and test equi pment and can discharge without detection. although the adsp-21365/6 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adsp-21365/6 preliminary technical data rev. pra | page 17 of 54 | september 2004 (pll). this pll-based clocking minimizes the skew between the system clock (clkin) signal and the processors internal clock (the clock source for the parallel port logic and i/o pads). note the definitions of various clock periods that are a function of clkin and the appropriate ratio control ( table 8 ). figure 5 shows core to clkin ratios of 6:1, 16:1 and 32:1 with external oscillator or crystal. no te that more ratios are possible and can be set through software using the power management control register (pmctl). fo r more information, see the adsp- 2136x sharc processor programming reference se the exact timing information given do not attemt to derive arameters from the addition or sutraction of others hile addition or sutraction would ield meaningful results for an individual device the va lues given in this data sheet reflect statistical variations and worst cases consequentl it is not meaningful to add arameters to derive longer times see igure 38 on age 3 under test conditions for voltage refer- ence levels switching characteristics secif how the rocessor changes its signals circuitr external to th e rocessor must e designed for comatiilit with these signal characteristics switching char- acteristics descrie what the rocessor will do in a given circumstance se switching charac teristics to ensure that an timing requirement of a device connected to the rocessor such as memor is satisfied timing requirements al to signals that are controlled cir- cuitr external to the rocessor such as the data inut for a read oeration timing requirements guarantee that the rocessor oerates correctl with other devices table 8. adsp-21365/6 clkout and cclk clock generation operation timing requirements description calculation clkin input clock 1/t ck cclk core clock 1/t cclk table 9. clock periods timing requirements description 1 1 where sr serial port-to-core clock ra tio (wide range, determined by sport clkdi) spir spi-to-core clock ratio (wide ra nge, determined by spibaud register) dai_px serial port clock spiclk spi clock t ck clkin clock period t cclk (processor) core clock period t pclk (peripheral) clock period = 2 t cclk t sclk serial port clock period = (t pclk ) sr t spiclk spi clock period = (t pclk ) spir figure 5. core clock and system clock relationship to clkin clkin cclk (core clock) pllilclk xtal xtal osc pll 6:1, 16:1, 32:1 clkout clk-cfg [1:0]
rev. pra | page 18 of 54 | september 2004 adsp-21365/6 preliminary technical data power-up sequencing the timing requirements for pr ocessor startup are given in table table 10. power up sequencing timing requirements (processor startup) parameter min max unit timing requirements t rstvdd reset low before v ddint /v ddext on 0 ns t ivddevdd v ddint on before v ddext C50 200 ms t clkvdd 1 clkin valid after v ddint /v ddext valid 0 200 ms t clkrst clkin valid before reset deasserted 10 2 s t pllrst pll control setup before reset deasserted 20 3 s switching characteristic t corerst core reset deasserted after reset deasserted 4096t ck + 2 t cclk 4, 5 1 valid v ddint /v ddext assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. voltage ra mp rates can vary from microseconds to h undreds of milliseconds depending on the de sign of the powe r supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case startup timing of crystal oscillators. refer to your crystal oscillator manufacturer's datasheet for startup time. assume a 25 ms maximum oscillator startup time if using the xtal pin and internal oscill ator circuit in conjunction with an ext ernal crystal. 3 based on clkin cycles 4 applies after the power-up sequence is complete. subseque nt resets require a minimum of 4 clkin cycles for reset to be held low in order to properly initialize and propagate default states at all i/o pins. 5 the 4096 cycle count depends on t srst specification in table 12 . if setup time is not met, 1 additional clkin cycle may be added to the core reset time, resulting in 4097 cycles maximum. figure 6. power-up sequencing clkin reset rstdd rstout ddet ddit prst rst dd iddedd -0 orerst
adsp-21365/6 preliminary technical data rev. pra | page 19 of 54 | september 2004 clock input clock signals the adsp-/ can use an external clock or a crystal see the clki pin description in table on page the program- mer can configure th e adsp-/ to use its internal clock generator by connecting the ne cessary components to clki and tal figure shows the component connections used for a crystal operating in fundamental mode ote that the clock rate is achieved using a mh crystal and a pll multiplier ratio (cclkclki achieves a clock speed of mh) to achieve the full core clock ra te, programs need to configure the multiplier bits in the pmctl register table 11. clock input parameter 333 mhz unit min max timing requirements t ck clkin period 18 1 1 applies only for clkcfg1C0 = 00 and defaul t values for pll control bits in pmctl. tbd 2 2 applies only for clkcfg1C0 = 01 and defaul t values for pll control bits in pmctl. ns t ckl clkin width low 7.5 1 tbd 2 ns t ckh clkin width high 7.5 1 tbd 2 ns t ckrf clkin rise/fall (0.4vC2.0v) tbd ns t cclk 3 3 any changes to pll control bits in the pmctl regis ter must meet core clock timing specification t cclk . cclk period 3.0 1 tbd ns figure 7. clock input clkin t ck t ckh t ckl figure 8. 333 mhz operation (fundamental mode crystal) clkin xtal c1 c2 x1 note: c1 and c2 are specific to crystal specified for x1. contact crystal manufacturer for details. crystal selection must comply with clkcfg1-0 = 10 or = 01. 1m
rev. pra | page 20 of 54 | september 2004 adsp-21365/6 preliminary technical data reset interrupts the following timing specification applies to the flag, flag, and flag pins when they are config ured as ir , ir , and ir interrupts table 12. reset parameter min max unit timing requirements t wrst 1 reset pulse width low 4t ck ns t srst reset setup before clkin low 8 ns 1 applies after the power-up sequence is comp lete. at power-up, the processor's internal ph ase-locked loop requires no more than 1 00 reset wrst srst table 13. interrupts parameter min max unit timing requirement t ipw irqx pulse width 2 t pclk +2 ns figure 10. interrupts dai_p20-1 flag2-0 (irq2-0) ipw
adsp-21365/6 preliminary technical data rev. pra | page 21 of 54 | september 2004 core timer the following timing specification applies to flag when it is configured as the core timer (ctimer) timer pwm_out cycle timing the following timing specification applies to timer, timer, and timer in pwm_out (pulse width modulation) mode timer signals are routed to the dai_p pins through the sru therefore, the timing specifications provided below are valid at the dai_p pins table 14. core timer parameter min max unit switching characteristic t wctim ctimer pulse width 4 t pclk C 1 ns figure 11. core timer flag3 (ctimer) t wctim table 15. timer pwm_out timing parameter min max unit switching characteristic t pwmo timer pulse width output 2 t pclk C 1 2(2 31 C 1) t pclk ns figure 12. timer pwm_out timing dai_p20-1 (timer2-0) t pwmo
rev. pra | page 22 of 54 | september 2004 adsp-21365/6 preliminary technical data timer wdth_cap timing the following timing specification applies to timer, timer, and timer in wdth_cap (pul se width count and capture) mode timer signals are routed to the dai_p pins through the sru therefore, the timing specification provided below are valid at the dai_p pins dai pin to pin direct routing for direct pin connections only (for example dai_pb_i to dai_pb_o) table 16. timer width capture timing parameter min max unit timing requirement t pwi timer pulse width 2 t pclk 2(2 31 C 1) t pclk ns figure 13. timer width capture timing dai_p20-1 (timer2-0) t pwi table 17. dai pin to pin routing parameter min max unit timing requirement t dpio delay dai pin input valid to dai output valid 1.5 10 ns figure 14. dai pin to pin direct routing dai_pn t dpio dai_pm
adsp-21365/6 preliminary technical data rev. pra | page 23 of 54 | september 2004 precision clock generator (direct pin routing) this timing is only valid when the sru is configured such that the precision clock generator (pcg) takes its inputs directly from the dai pins (via pin buffers) and sends its outputs directly to the dai pins for the other ca ses, where the pcgs inputs and outputs are not directly routed to/from dai pins (via pin buffers) there is no timing data available all timing param- eters and switching characteristic s apply to external dai pins (dai_p dai_p) table 18. precision clock generator (direct pin routing) parameter min max unit timing requirement s t pcgiw input clock period 24 t strig pcg trigger setup before falling edge of pcg input clock 2 ns t htrig pcg trigger hold after falling edge of pcg input clock 2 ns switching characteristics t dpcgio pcg output clock and frame sync active edge delay after pcg input clock 2.5 10 ns t dtrig pcg output clock and frame sync delay after pcg trigger 2.5 + 2.5 t pcgow 10 + 2.5 t pcgow ns t pcgow output clock period 48 figure 15. precision clock generator (direct pin routing) dai_pn pcg_trigx_i t strig dai_pm pcg_extx_i (clkin) dai_py pcg_clkx_o dai_pz pcg_fsx_o t htrig t dpcgio t dtrig t pcgiw t pcgow
rev. pra | page 24 of 54 | september 2004 adsp-21365/6 preliminary technical data flags the timing specifications provided below apply to the flag and dai_p pins, the parallel port, and the serial peripheral interface (spi) see table , pin descri ptions, on page for more information on flag use table 19. flags parameter min max unit timing requirement t fipw flag3C0 in pulse width 2 t pclk + 3 ns switching characteristic t fopw flag3C0 out pulse width 2 t pclk C 1 ns figure 16. flags dai_p20-1 (flag3-0 in ) (ad15-0) t fipw dai_p20-1 (flag3-0 out ) (ad15-0) t fopw
adsp-21365/6 preliminary technical data rev. pra | page 25 of 54 | september 2004 memory readparallel port use these specifications for asyn chronous interfacing to memo- ries (and memory-mapped peripherals) when the adsp-/ is accessing external memory space table 20. 8-bit memory read cycle parameter min max unit timing requirements t drs address/data 7C0 setup before rd high 3.3 ns t drh address/data 7C0 hold after rd high 0 ns t dad address 15C8 to data valid d + t pclk C 5 ns switching characteristics t alew ale pulse width 2 t pclk C 2.0 ns t adas 1 address/data 15C0 setup before ale deasserted t pclk C 2.5 ns t rrh delay between rd rising edge to next falling edge. h + t pclk C 1 ns t alerw ale deasserted to read asserted 2 t pclk C 2 ns t rwale read deasserted to ale asserted f + h + 0.5 ns t adah 1 address/data 15C0 hold after ale deasserted t pclk C 0.8 t alehz 1 ale deasserted to address/data7C0 in high z t pclk C 0.8 t pclk ns t rw rd pulse width d C 2 ns t rddrv rd address drive after read high f + h + t pclk C 1 ns t adrh address/data 15C8 hold after rd high h ns d = (data cycle duration = the value set by th e ppdur bits (5C1) in the ppctl register) t pclk h = t pclk (if a hold cycle is specified, else h = 0) f = 7 x t pclk (if flash_mode is set else f = 0) t pclk = (peripheral) clock period = 2 t cclk 1 on reset, ale is an active high cycle. however, it can be configured by soft ware to be active low. figure 17. read cycle for 8-bit memory timing valid address valid address ad15-8 t adas valid address ad7-0 t alew ale rd rw wr d dr drs dr dd erw rwe id dt id ddress rddr e id ddress id ddress id dt rr
rev. pra | page 26 of 54 | september 2004 adsp-21365/6 preliminary technical data table 21. 16-bit memory read cycle parameter min max unit timing requirements t drs address/data 15C0 setup before rd high 3.3 ns t drh address/data 15C0 hold after rd high 0 ns switching characteristics ns t alew ale pulse width 2 t pclk C 2 ns t adas 1 address/data 15C0 setup before ale deasserted t pclk C 2.5 ns t alerw ale deasserted to read asserted 2 t pclk C 2 ns t rrh delay between rd rising edge to next falling edge. h + t pclk C 1 ns t rwale read deasserted to ale asserted f + h + 0.5 ns t rddrv rd address drive after read high f + h + t pclk C 1 ns t adah 1 address/data 15C0 hold after ale deasserted t pclk C 0.8 ns t alehz 1 ale deasserted to address/data15C0 in high z t pclk C 0.8 ns t rw rd pulse width d C 2 ns d = (data cycle duration = the value set by th e ppdur bits (5C1) in the ppctl register) t pclk h = t pclk (if a hold cycle is specified, else h = 0) f = 7 x t pclk (if flash_mode is set else f = 0) 1 on reset, ale is an active high cycle. however, it can be configured by soft ware to be active low. figure 18. read cycle for 16-bit memory timing ad15-0 wr drs dr rddr e d ds id ddress id dt id ddress ew rw erw rwe rr e rd
adsp-21365/6 preliminary technical data rev. pra | page 27 of 54 | september 2004 memory writeparallel port use these specifications for asyn chronous interfacing to memo- ries (and memory-mapped peripherals) when the adsp-/ is accessing external memory space table 22. 8-bit memory write cycle parameter min max unit switching characteristics t alew ale pulse width 2 t pclk C 2 ns t adas 1 address/data 15C0 setup before ale deasserted t pclk C 2.5 ns t alerw ale deasserted to read/write asserted 2 t pclk C 2 ns t rwale write deasserted to ale asserted h + 0.5 ns t wrh delay between wr rising edge to next wr falling edge f + h + t pclk C 2 ns t adah 1 address/data 15C0 hold after ale deasserted t pclk C 0.5 ns t ww wr pulse width d C f C 2 ns t adwl address/data 15C8 to wr low t pclk C 1.5 ns t adwh address/data 15C8 hold after wr high h ns t dws address/data 7C0 setup before wr high d C f + t pclk C 4 ns t dwh address/data 7C0 hold after wr high h ns t dawh address/data to wr high d C f + t pclk C 4 ns d = (data cycle duration = the value set by th e ppdur bits (5C1) in the ppctl register) t pclk h = t pclk (if a hold cycle is specified, else h = 0) f = 7 x t pclk (if flash_mode is set else f = 0) 1 on reset, ale is an active high cycle. however, it can be configured by soft ware to be active low. figure 19. write cycle for 8-bit memory timing ad15-8 valid address valid address t adas ad7-0 ale rd wr d dw dw id dt dw wr rwe id ddress id dt ew erw ww dws dw id ddress
rev. pra | page 28 of 54 | september 2004 adsp-21365/6 preliminary technical data table 23. 16-bit memory write cycle parameter min max unit switching characteristics t alew ale pulse width 2 t pclk C 2 ns t adas 1 address/data 15C0 setup before ale deasserted t pclk C 2.5 ns t alerw ale deasserted to write asserted 2 t pclk C 2 ns t rwale write deasserted to ale asserted h + 0.5 ns t wrh delay between wr rising edge to next wr falling edge f + h + t pclk C 2 ns t adah 1 address/data 15C0 hold after ale deasserted t pclk C 0.5 ns t ww wr pulse width d C f C 2 ns t alehz 1 ale deasserted to address/data15C0 in high z t pclk C 1.5 ns t dws address/data 15C0 setup before wr high d C f + t pclk C 4 ns t dwh address/data 15C0 hold after wr high h ns d = (data cycle duration = the value set by th e ppdur bits (5C1) in the ppctl register) t pclk h = t pclk (if a hold cycle is specified, else h = 0) f = 7 x t pclk (if flash_mode is set else f = 0) 1 on reset, ale is an active high cycle. however, it can be configured by soft ware to be active low. figure 20. write cycle for 16-bit memory timing ad15-0 valid address valid data t adas ale rd wr d wr rwe ew erw ww dws dw id dt
adsp-21365/6 preliminary technical data rev. pra | page 29 of 54 | september 2004 serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed ) frame sync delay and frame sync setup and hold, ) data delay and data setup and hold, and ) sclk width serial port signals (sclk, fs, data channel a,/data channel b) are routed to the dai_p pins using the sru therefore, the timing specifications provided below are valid at the dai_p pins table 24. serial portsexternal clock parameter min max unit timing requirements t sfse 1 fs setup before sclk (externally generated fs in either transmit or receive mode) 2.5 ns t hfse 1 fs hold after sclk (externally generated fs in either transmit or receive mode) 2.5 ns t sdre 1 receive data setup before receive sclk 2.5 ns t hdre 1 receive data hold after sclk 2.5 ns t sclkw sclk width 24 ns t sclk sclk period 48 ns switching characteristics t dfse 2 fs delay after sclk (internally generated fs in either transmit or receive mode) 7 ns t hofse 2 fs hold after sclk (internally generated fs in either transmit or receive mode) 2 ns t ddte 2 transmit data delay after transmit sclk 7 ns t hdte 2 transmit data hold after transmit sclk 2 ns 1 referenced to sample edge. 2 referenced to drive edge. table 25. serial portsinternal clock parameter min max unit timing requirements t sfsi 1 fs setup before sclk (externally generated fs in either transmit or receive mode) 7 ns t hfsi 1 fs hold after sclk (externally generated fs in either transmit or receive mode) 2.5 ns t sdri 1 receive data setup before sclk 7 ns t hdri 1 receive data hold after sclk 2.5 ns switching characteristics t dfsi 2 fs delay after sclk (internally generated fs in transmit mode) 3 ns t hofsi 2 fs hold after sclk (internally generated fs in transmit mode) C1.0 ns t dfsi 2 fs delay after sclk (internally generated fs in receive or mode) 3 ns t hofsi 2 fs hold after sclk (internally generated fs in receive mode) C1.0 ns t ddti 2 transmit data delay after sclk 3 ns t hdti 2 transmit data hold after sclk C1.0 ns t sclkiw transmit or receive sclk width 0.5t sclk C 2 0.5t sclk + 2 ns 1 referenced to the sample edge. 2 referenced to drive edge.
rev. pra | page 30 of 54 | september 2004 adsp-21365/6 preliminary technical data table 26. serial portsenable and three-state parameter min max unit switching characteristics t ddten 1 data enable from external transmit sclk 2 ns t ddtte 1 data disable from external transmit sclk 7 ns t ddtin 1 data enable from internal transmit sclk C1 ns 1 referenced to drive edge. table 27. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse 1 data delay from late external transmit fs or external receive fs with mce = 1, mfd = 0 7 ns t ddtenfs 1 data enable for mce = 1, mfd = 0 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justified sample pair as well as dsp serial mode, and mce = 1, mfd = 0. figure 21. external late frame sync 1 1 this figure reflects changes made to su pport left-justified sample pair mode. drive sample drive dai_p20-1 (sclk) dai_p20-1 (fs) dai_p20-1 (data channel a/b) drive sample drive late external transmit fs external receive fs with mce = 1, mfd = 0 1st bit 2nd bit dai_p20-1 (sclk) dai_p20-1 (fs) 1st bit 2nd bit t hfse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i dai_p20-1 (data channel a/b) note serial port signals (sclk, fs, data channel a/b ) are routed to the dai_p20-1 pins using the sru. the timing specifications provided here are valid at the dai_p20-1 pins. t hfse/i
adsp-21365/6 preliminary technical data rev. pra | page 31 of 54 | september 2004 figure 22. serial ports drive edge dai_p20-1 sclk (int) drive edge drive edge sclk dai_p20-1 sclk (ext) t ddtte t ddten t ddtin dai_p20-1 (data channel a/b) dai_p20-1 (data channel a/b) dai_p20-1 (sclk) dai_p20-1 (fs) drive edge sample edge data receive internal clock data receive e x ternal clock drive edge sample edge note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t sdri t hdri t sfsi t hfsi t dfsi t hofsi t sclkiw t sdre t hdre t sfse t hfse t dfse t sclkw t hofse dai_p20-1 (data channel a/b) t ddti drive edge sample edge data transmit internal clock t sfsi t hfsi t dfsi t hofsi t sclkiw t hdti note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t ddte drive edge sample edge data transmit external clock t sfse t hfse t dfse t hofse t sclkw t hdte dai_p20-1 (sclk) dai_p20-1 (fs) dai_p20-1 (data channel a/b) dai_p20-1 (sclk) dai_p20-1 (fs) dai_p20-1 (data channel a/b) dai_p20-1 (sclk) dai_p20-1 (fs) dai_p20-1 (data channel a/b)
rev. pra | page 32 of 54 | september 2004 adsp-21365/6 preliminary technical data input data port the timing requirements for the idp are given in table idp signals (sclk, fs, sdata) are routed to the dai_p pins using the sru therefore, the ti ming specifications provided below are valid at the dai_p pins table 28. idp parameter min max unit timing requirements t sifs 1 fs setup before sclk rising edge 2.5 ns t sihfs 1 fs hold after sclk rising edge 2.5 ns t sisd 1 sdata setup before sclk rising edge 2.5 ns t sihd 1 sdata hold after sclk rising edge 2.5 ns t idpclkw clock width 9 ns t idpclk clock period 24 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcg's input can be either clkin or any of the dai pins. figure 23. idp master timing dai_p20-1 (sclk) dai_p20-1 (fs) sample edge t sisd t sihd t sisfs t sihfs t sisclkw dai_p20-1 (sdata)
adsp-21365/6 preliminary technical data rev. pra | page 33 of 54 | september 2004 parallel data acquisition port (pdap) the timing requirements for the pdap are provided in table pdap is the parallel mode operation of channel of the idp for details on the oper ation of the idp, see the idp chapter of the adsp-2136x sharc proc essor hardware refer- ence ote that the most significant 16 its of external pdap data can e rovided through either the arallel ort ad1 or the dap2 ins the remainin g its can onl e sourced through dap1 the timing elow is valid at the dap21 ins or at the ad1 ins table 29. parallel data acquisition port (pdap) parameter min max unit timing requirements t spclken 1 pdap_clken setup before pdap_clk sample edge 2.5 ns t hpclken 1 pdap_clken hold after pdap_clk sample edge 2.5 ns t pdsd 1 pdap_dat setup before sclk pdap_clk sample edge 2.5 ns t pdhd 1 pdap_dat hold after sclk pdap_clk sample edge 2.5 ns t pdclkw clock width 7 ns t pdclk clock period 24 ns switching characteristics t pdhldd delay of pdap strobe after last pdap_clk capture edge for a word 2 t cclk ns t pdstrb pdap strobe pulse width 1 t cclk C 1 ns 1 source pins of data are addr7C0, data7C0, or dai pins. source pin s for sclk and fs are: 1) dai pins, 2) clkin through pcg, or 3) dai pins through pcg. figure 24. pdap timing dai_p20-1 (pdap_clk) sample edge t pdsd t pdhd t spclken t hpclken t pdclkw data dai_p20-1 (pdap_clken) t pdstrb t pdhldd dai_p20-1 (pdap_strobe) t pdclk
rev. pra | page 34 of 54 | september 2004 adsp-21365/6 preliminary technical data sample rate converterserial input port the src input signals (sclk, fs , and sdata) are routed from the dai_p pins using the sru therefore, the timing spec- ifications provided in table are valid at the dai_p pins table 30. src, serial input port parameter min max unit timing requirements t sifs 1 fs setup before sclk rising edge 4 ns t sihfs 1 fs hold after sclk rising edge 5.5 ns t sisd 1 sdata setup before sclk rising edge 4 ns t sihd 1 sdata hold after sclk rising edge 5.5 ns t idpclkw clock width 9 ns t idpclk clock period 20 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcg's input can be either clkin or any of the dai pins. figure 25. src serial input port timing dai_p20-1 (sclk) dai_p20-1 (fs) sample edge t sisd t sihd t sisfs t sihfs t idpclkw dai_p20-1 (sdata)
adsp-21365/6 preliminary technical data rev. pra | page 35 of 54 | september 2004 sample rate converterserial output port for the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to sclk on the output port the serial data output, sdata, has a hold time and delay specification with regard to sclk ote that sclk rising edge is the sampling edge and the falling edge is the drive edge table 31. src, serial output port parameter min max unit timing requirements t sifs 1 fs setup before sclk rising edge 4 ns t sihfs 1 fs hold before sclk rising edge 5.5 ns t srctdd 1 transmit data delay afte r sclk falling edge 7 ns t srctdh 1 transmit data hold after sclk falling edge 2 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcg's input can be either clkin or any of the dai pins. figure 26. src serial output port timing dai_p20-1 (sclk) dai_p20-1 (fs) sample edge t sifs t sihfs t sisclkw dai_p20-1 (sdata) t srctdd t srctdh
rev. pra | page 36 of 54 | september 2004 adsp-21365/6 preliminary technical data spdif transmitter serial data input to the spdif transmitter can be formatted as left ustified, i s or right ustified with wo rd widths of , , , or bits the following sect ions provide timing for the transmitter spdif transmitterserial input waveforms figure 27 shows the right-ustified mode. lrclk is hi for the left channel and lo for the right channel. data is valid on the rising edge of sclk. the msb is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit output mode) from an lrclk transition, so that when there are 64 sclk periods per lrclk period, the lsb of the data will be right-ustified to the next lrclk transition. figure 28 shows the default i2s-ustified mode. lrclk is lo for the left channel and hi for the right channel. data is valid on the rising edge of sclk. the msb is left-ustified to an lrclk transition but with a single sclk period delay. figure 29 shows the left-ustified mode . lrclk is hi for the left channel and lo for the right channel. data is valid on the rising edge of sclk. the msb is left-us tified to an lrclk transition with no msb delay. figure 27. right-justified mode lrclk sclk sdata left channel right channel msb-1 msb-2 lsb2 lsb1 lsb msb msb-1 msb-2 lsb2 lsb1 lsb lsb msb figure 28. i 2 s-justified mode msb-1 msb-2 lsb2 lsb1 lsb lrclk sclk sdata left channel right channel msb msb-1 msb-2 lsb2 lsb1 lsb msb msb figure 29. left-justified mode lrclk sclk sdata left channel right channel ms b-1 ms b-2 lsb2 lsb1 lsb msb msb-1 msb-2 lsb2 lsb1 lsb msb msb1 msb
adsp-21365/6 preliminary technical data rev. pra | page 37 of 54 | september 2004 spdif transmitter input data timing the timing requirements for the input port are given in table 32 . input signals (sclk, fs, sdata) are routed to the dai_p20C1 pins using the sru. therefore, the timing specifica- tions provided below are va lid at the dai_p20C1 pins. over sampling clock (txclk) switching characteristics spdif transmitter has an over sampling clock. this txclk input is divided down to generate the biphase clock. table 32. spdif transmitter input data timing parameter min max unit timing requirements t sifs 1 fs setup before sclk rising edge 4 ns t sihfs 1 fs hold after sclk rising edge 5.5 ns t sisd 1 sdata setup before sclk rising edge 4 ns t sihd 1 sdata hold after sclk rising edge 5.5 ns t sisclkw clock width 9 ns t sisclk clock period 20 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcg's input can be either clkin or any of the dai pins. figure 30. spdif transmitter input timing dai_p20-1 (sclk) dai_p20-1 (fs) sample edge t sisd t sihd t sisfs t sihfs t sisclkw dai_p20-1 (sdata) table 33. over sampling clock (t xclk) switching characteristics parameter min max unit txclk frequency for txclk = 768 fs 147.5 mhz txclk frequency for txclk = 512 fs 98.4 mhz txclk frequency for txclk = 384 fs 73.8 mhz txclk frequency for txclk = 256 fs 49.2 mhz frame rate 192.0 mhz
rev. pra | page 38 of 54 | september 2004 adsp-21365/6 preliminary technical data spdif receiver the following sections describe timing as it relates to the spdif receiver internal digital pll mode in internal digital phase-locked loop mode the internal pll (digital pll) generates the 512 fs clock. table 34. spdif receiver internal digital pll mode timing parameter min max unit switching characteristics t dfsi lrclk delay after sclk 5 ns t hofsi lrclk hold after sclk C2 ns t ddti transmit data delay after sclk 5 ns t hdti transmit data hold after sclk C2 ns t sclkiw 1 transmit sclk width 40 ns t cclk core clock period 5 ns 1 sclk frequency is 64 x fs where fs = the frequency of lrclk. figure 31. spdif receiver internal digital pll mode timing drive edge sample edge dai_p20-1 (sclk) dai_p20-1 (fs) dai_p20-1 (data channel a/b) t sclkiw t dfsi t ddti t hofsi t hdti t sfsi t hfsi
adsp-21365/6 preliminary technical data rev. pra | page 39 of 54 | september 2004 external pll mode in external pll mode internal digital pll is disabled and the receiver runs on the pll that is connected to the processor externally. this external p ll generates the 512 x fs clock (mclk) from the reference cl ock (lrclk) and gives it to spdif receiver. table 35. spdif receiver external pll mode timing parameter min max unit timing requirements t mcp mclk period 10 ns fmclk mclk frequency (1/t mcp )100mhz t bdm sclk propagation delay from mclk to the falling edge 30 ns t ldm lrclk propagation delay from mclk 30 ns t ddp data propagation delay from mclk 30 ns t dds data output setup to sclk 1/2 sclk period ns t ddh data output hold from sclk 1/2 sclk period ns figure 32. spdif receiver external pll mode timing t ldm t bdm t dds msb t ddh mclk input (not to scale) bclk output lrclk output sdata output i 2 s-justified mode t ddp t dds t ddh t ddp msb lsb t ddh t dds sdata output right-justified mode
rev. pra | page 40 of 54 | september 2004 adsp-21365/6 preliminary technical data spi interfacemaster the adsp-/ contains two spi ports the primary has dedicated pins and the secondary is available through the dai the timing provided in table and table on page applies to both table 36. spi interface protocol master switching and timing specifications parameter min max unit timing requirements t sspidm data input valid to spiclk edge (data input set-up time) 8 ns t hspidm spiclk last sampling edge to data input not valid 2 ns switching characteristics t spiclkm serial clock cycle 8 t pclk ns t spichm serial clock high period 4 t pclk ns t spiclm serial clock low period 4 t pclk C 2 ns t ddspidm spiclk edge to data out valid (data out delay time) 0 t hdspidm spiclk edge to data out not valid (data out hold time) 2 ns t sdscim flag3C0in (spi device select) low to first spiclk edge 4 t pclk C 2 ns t hdsm last spiclk edge to flag3C0in high 4 t pclk C 1 ns t spitdm sequential transfer delay 4 t pclk C 1 ns figure 33. spi master timing lsb valid msb valid t sspidm t hspidm t hdspidm lsb msb t hsspidm t ddspidm mosi (output) miso (input) flag3-0 (output) spiclk (cp = 0) (output) spiclk (cp = 1) (output) t spichm t spiclm t spiclm t spiclkm t spichm t hdsm t spitdm t hdspidm lsb valid lsb msb msb valid t hspidm t ddspidm mosi (output) miso (input) t sspidm cphase=1 cphase=0 t sdscim t sspidm
adsp-21365/6 preliminary technical data rev. pra | page 41 of 54 | september 2004 spi interfaceslave table 37. spi interface protocol slave switching and timing specifications parameter min max unit timing requirements t spiclks serial clock cycle 4 t pclk ns t spichs serial clock high period 2 t pclk ns t spicls serial clock low period 2 t pclk C 2 ns t sdsco spids assertion to first spiclk edge cphase = 0 cphase = 1 2 t pclk 2 t pclk ns t hds last spiclk edge to spids not asserted, cphase = 0 2 t pclk ns t sspids data input valid to spiclk edge (data input set-up time) 2 ns t hspids spiclk last sampling edge to data input not valid 2 ns t sdppw spids deassertion pulse width (cphase=0) 2 t pclk ns switching characteristics t dsoe spids assertion to data out active 0 4 ns t dsdhi spids deassertion to data high impedance 0 4 ns t ddspids spiclk edge to data out valid (data out delay time) 9.4 ns t hdspids spiclk edge to data out not valid (data out hold time) 2 t pclk ns t dsov spids assertion to data out valid (cphase=0) 5 t pclk ns figure 34. spi slave timing t hspids t ddspids t dsdhi lsb msb msb valid t dsoe t ddspids t hdlsbs miso (output) mosi (input) t sspids spids (iput) spi (p 0) (iput) spi (p ) (iput) sdso spis spis spis spis ds spis sspids spids dsdi s id s s id dsoe ddspids iso (output) osi (iput) sspids s id s pse pse0 sdppw dso dss
rev. pra | page 42 of 54 | september 2004 adsp-21365/6 preliminary technical data jtag test access port and emulation table 38. jtag test access port and emulation parameter min max unit timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys 1 system inputs setup before tck low 7 ns t hsys 1 system inputs hold after tck low 18 ns t trstw trst pulse width 4t ck ns switching characteristics t dtdo tdo delay from tck low 7 ns t dsys 2 system outputs delay after tck low 10 ns 1 system inputs = ad15C0, spids , clkcfg1C0, reset , bootcfg1C0, miso, mosi, spiclk, dai_px, flag3C0. 2 system outputs = miso, mosi, spiclk, dai_px, ad15C0, rd , wr , flag3C0, clkout, emu , ale. figure 35. ieee 1149.1 jtag test access port tck tms tdi tdo system inputs system outputs t stap t tck t htap t dtdo t ssys t hsys t dsys
adsp-21365/6 preliminary technical data rev. pra | page 43 of 54 | september 2004 output drive currents figure 36 shows typical i-v characteri stics for the output driv- ers of the adsp-21365/6. the curv es represent the current drive capability of the output drivers as a function of output voltage. test conditions the ac signal specifications (timing parameters) appear table 12 on page 20 through table 38 on page 42 . these include output disable time, output enable time, and capacitive loading. the timing specifications for the sharc apply for the voltage reference levels in figure 37 . timing is measured on signals wh en they cross the 1.5 v level as described in figure 38 . all delays (in nanoseconds) are mea- sured between the point that the first signal reaches 1.5 v and the point that the second signal reaches 1.5 v. capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 37 ). figure 41 shows graphically how output delays and holds vary with load capacitance. the graphs of figure 39 , figure 40 , and figure 41 may not be linear outside the ranges shown for typical output delay vs. load capacitance and typical output rise time (20-80, v=min) vs. load capacitance. figure 36. adsp-21365/6 typical drive figure 37. equivalent device loading for ac measurements (includes all fixtures) figure 38. voltage reference levels for ac measurements sweep (v ddext )voltage(v) -20 03.5 0.5 1 1.5 2 2.5 3 0 -40 -30 20 40 -10 s o u r c e ( v d d e x t ) c u r r e n t ( m a ) v ol 3.11v, 125 c 3.3v, 25 c 3.47v, -45 c v oh 30 10 3.11v, 125 c 3.3v, 25 c 3.47v, -45 c 1.5v 30pf to output pin 50 input or output 1.5v 1.5v figure 39. typical output rise/fall time (20%-80%, v ddext = max) figure 40. typical output rise/fall time (20%-80%, v ddext =min) load capacitance (pf) 8 0 0 100 250 12 4 2 10 6 r i s e a n d f a l l t i m e s ( n s ) 200 150 50 fall y = 0.0467x + 1.6323 y = 0.045x + 1.524 rise load capacitance (pf) 12 0 50 100 150 200 250 10 8 6 4 r i s e a n d f a l l t i m e s ( n s ) 2 0 rise fall y = 0.049x + 1.5105 y = 0.0482x + 1.4604
rev. pra | page 44 of 54 | september 2004 adsp-21365/6 preliminary technical data thermal characteristics the adsp-21365/6 processor is rated for performance to a maximum junction temperature of 125c. table 39 through table 42 airflow measurements comply with jedec standards jesd51-2 and jesd51-6 and the junction-to- board measurement complies wi th jesd51-8. test board and thermal via design comply wi th jedec standards jesd51-9 (mini-bga) and jesd51-5 (integrated heatsink lqfp). the junction-to-case measurement complies with mil- std-883. all measurements use a 2s2p jedec test board. industrial applications using the mini-bga package require thermal vias, to an embedded grou nd plane, in the pcb. refer to jedec standard jesd51-9 for printed circuit board thermal ball land and thermal via design information. industrial applica- tions using the lqfp package re quire thermal trace squares and thermal vias, to an embedded gr ound plane, in the pcb. the bottom side heat slug must be soldered to the thermal trace squares. refer to jedec standard jesd51-5 for more information. to determine the junction temper ature of the device while on the application pcb, use: where: t j = junction temperature t j t case jt p d () + = table 39. thermal characteri stics for 136 ball mini-bga (no thermal vias in pcb) parameter condition typical unit ja airflow = 0 m/s 25.20 c/w jma airflow = 1 m/s 21.70 c/w jma airflow = 2 m/s 20.80 c/w jc 5.00 c/w jt airflow = 0 m/s 0.140 c/w jmt airflow = 1 m/s 0.330 c/w jmt airflow = 2 m/s 0.410 c/w table 40. thermal characteri stics for 136 ball mini-bga (thermal vias in pcb) parameter condition typical unit ja airflow = 0 m/s 22.50 c/w jma airflow = 1 m/s 19.30 c/w jma airflow = 2 m/s 18.40 c/w jc 5.00 c/w jt airflow = 0 m/s 0.130 c/w jmt airflow = 1 m/s 0.300 c/w jmt airflow = 2 m/s 0.360 c/w table 41. thermal characterist ics for 144-lead integrated heatsink (intChs) lqfp (with heat slug not soldered to pcb) parameter condition typical unit ja airflow = 0 m/s 26.08 c/w jma airflow = 1 m/s 24.59 c/w jma airflow = 2 m/s 23.77 c/w jc 6.83 c/w jt airflow = 0 m/s 0.236 c/w jmt airflow = 1 m/s 0.427 c/w jmt airflow = 2 m/s 0.441 c/w t j t a ja p d () + =
adsp-21365/6 preliminary technical data rev. pra | page 45 of 54 | september 2004 table 42. thermal characteristics for 144-lead integrated heatsink (intChs) lqfp (with heat slug soldered to pcb) parameter condition typical unit ja airflow = 0 m/s 16.50 c/w jma airflow = 1 m/s 15.14 c/w jma airflow = 2 m/s 14.35 c/w jc 6.83 c/w jt airflow = 0 m/s 0.129 c/w jmt airflow = 1 m/s 0.255 c/w jmt airflow = 2 m/s 0.261 c/w
rev. pra | page 46 of 54 | september 2004 adsp-21365/6 preliminary technical data 136-ball bga pin configurations the following table shows th e adsp-21365/6?s pin names and their default function after reset (in parentheses). table 43. 136-ball mini-b ga pin assignments pin name bga pin pin name bga pin pin name bga pin pin name bga pin clkcfg0 a01 clkcfg1 b01 bootcfg1 c01 v ddint d01 xtal a02 gnd b02 bootcfg0 c02 gnd d02 tms a03 v ddext b03 gnd c03 gnd d04 tck a04 clkin b04 gnd c12 gnd d05 tdi a05 trst b05 gnd c13 gnd d06 clkout a06 a vss b06 v ddint c14 gnd d09 tdo a07 a vdd b07 gnd d10 emu a08 v ddext b08 gnd d11 mosi a09 spiclk b09 gnd d13 miso a10 reset b10 v ddint d14 spids a11 v ddint b11 v ddint a12 gnd b12 gnd a13 gnd b13 gnd a14 gnd b14 v ddint e01 flag1 f01 ad7 g01 ad6 h01 gnd e02 flag0 f02 v ddint g02 v ddext h02 gnd e04 gnd f04 v ddext g13 dai_p18 (sd5b) h13 gnd e05 gnd f05 dai_p19 (sclk45) g14 dai_p17 (sd5a) h14 gnd e06 gnd f06 gnd e09 gnd f09 gnd e10 gnd f10 gnd e11 gnd f11 gnd e13 flag2 f13 flag3 e14 dai_p20 (sfs45) f14
adsp-21365/6 preliminary technical data rev. pra | page 47 of 54 | september 2004 ad5 j01 ad3 k01 ad2 l01 ad0 m01 ad4 j02 v ddint k02 ad1 l02 wr m02 gnd j04 gnd k04 gnd l04 gnd m03 gnd j05 gnd k05 gnd l05 gnd m12 gnd j06 gnd k06 gnd l06 dai_p12 (sd3b) m13 gnd j09 gnd k09 gnd l09 dai_p13 (sclk23) m14 gnd j10 gnd k10 gnd l10 gnd j11 gnd k11 gnd l11 v ddint j13 gnd k13 gnd l13 dai_p16 (sd4b) j14 dai_p15 (sd4a) k14 dai_p14 (sfs23) l14 ad15 n01 ad14 p01 ale n02 ad13 p02 rd n03 ad12 p03 v ddint n04 ad11 p04 v ddext n05 ad10 p05 ad8 n06 ad9 p06 v ddint n07 dai_p1 (sd0a) p07 dai_p2 (sd0b) n08 dai_p3 (sclk0) p08 v ddext n09 dai_p5 (sd1a) p09 dai_p4 (sfs0) n10 dai_p6 (sd1b) p10 v ddint n11 dai_p7 (sclk1) p11 v ddint n12 dai_p8 (sfs1) p12 gnd n13 dai_p9 (sd2a) p13 dai_p10 (sd2b) n14 dai_p11 (sd3a) p14 table 43. 136-ball mini-bga pi n assignments (continued) pin name bga pin pin name bga pin pin name bga pin pin name bga pin
rev. pra | page 48 of 54 | september 2004 adsp-21365/6 preliminary technical data figure 42. 136-ball mini-bga pin assignments (bottom view, summary) a vss v ddint v ddext i/o signals a vdd gnd* *use the center block of ground pins to provide thermal pathways to your printed circuit board?s ground plane. key 1 2 3 4 5 6 7 8 9 10 11 12 14 13 p n m l k j h g f e d c b a
adsp-21365/6 preliminary technical data rev. pra | page 49 of 54 | september 2004 144-lead lqfp pin configurations the following table shows th e adsp-21365/6s pin names and their default function after reset (in parentheses). table 44. 144-lead lqfp pin assignments pin name lqfp pin no. pin name lqfp pin no. pin name lqfp pin no. pin name lqfp pin no. v ddint 1v ddint 37 v ddext 73 gnd 109 clkcfg0 2 gnd 38 gnd 74 v ddint 110 clkcfg1 3 rd 39 v ddint 75 gnd 111 bootcfg0 4 ale 40 gnd 76 v ddint 112 bootcfg1 5 ad15 41 dai_p10 (sd2b) 77 gnd 113 gnd 6 ad14 42 dai_p11 (sd3a) 78 v ddint 114 v ddext 7 ad13 43 dai_p12 (sd3b) 79 gnd 115 gnd 8 gnd 44 dai_p13 (sclk23) 80 v ddext 116 v ddint 9v ddext 45 dai_p14 (sfs23) 81 gnd 117 gnd 10 ad12 46 dai_p15 (sd4a) 82 v ddint 118 v ddint 11 v ddint 47 v ddint 83 gnd 119 gnd 12 gnd 48 gnd 84 v ddint 120 v ddint 13 ad11 49 gnd 85 reset 121 gnd 14 ad10 50 dai_p16 (sd4b) 86 spids 122 flag0 15 ad9 51 dai_p17 (sd5a) 87 gnd 123 flag1 16 ad8 52 dai_p18 (sd5b) 88 v ddint 124 ad7 17 dai_p1 (sd0a) 53 dai_p19 (sclk45) 89 spiclk 125 gnd 18 v ddint 54 v ddint 90 miso 126 v ddint 19 gnd 55 gnd 91 mosi 127 gnd 20 dai_p2 (sd0b) 56 gnd 92 gnd 128 v ddext 21 dai_p3 (sclk0) 57 v ddext 93 v ddint 129 gnd 22 gnd 58 dai_p20 (sfs45) 94 v ddext 130 v ddint 23 v ddext 59 gnd 95 a vdd 131 ad6 24 v ddint 60 v ddint 96 a vss 132 ad5 25 gnd 61 flag2 97 gnd 133 ad4 26 dai_p4 (sfs0) 62 flag3 98 clkout 134 v ddint 27 dai_p5 (sd1a) 63 v ddint 99 emu 135 gnd 28 dai_p6 (sd1b) 64 gnd 100 tdo 136 ad3 29 dai_p7 (sclk1) 65 v ddint 101 tdi 137 ad2 30 v ddint 66 gnd 102 trst 138 v ddext 31 gnd 67 v ddint 103 tck 139 gnd 32 v ddint 68 gnd 104 tms 140 ad1 33 gnd 69 v ddint 105 gnd 141 ad0 34 dai_p8 (sfs1) 70 gnd 106 clkin 142 wr 35 dai_p9 (sd2a) 71 v ddint 107 xtal 143 v ddint 36 v ddint 72 v ddint 108 v ddext 144
rev. pra | page 50 of 54 | september 2004 adsp-21365/6 preliminary technical data package dimensions the adsp-21365/6 is available in a 136-ball mini-bga package and a 144-lead integrated heatsink lqfp package. figure 43. 136-ball mini-bga (bc-136-2) seating plane 0.25 min detail a 0.50 0.45 0.40 (ball diameter) detail a 1.70 max 1. dimensions are in milimeters (mm). 2. the actual position of the ball grid is within 0.15 mm of its ideal position relative to the package edges. 3. the actual position of each ball is within 0.08 mm of its ideal position relative to the ball grid. 4. compliant to jedec standard mo-205-ae, except for the ball diameter. 5. center dimensions are nominal. a b c d e f g h j k l m n p 10987654321 13 14 11 12 0.80 bsc typ 10.40 bsc sq pin a1 indicator bottom view top view 12.00 bsc sq 0.12 max (ball coplanarity) 0.80 bsc typ 0.80 bsc typ
adsp-21365/6 preliminary technical data rev. pra | page 51 of 54 | september 2004 ordering guide analog devices offers a wide va riety of audio algorithms and combinations to ru n on the adsp-21365/6 processor. these products are sold as part of a chip set, bundled with necessary application software under special part numbers. for a complete list, visit our web site at www.analog.com/sharc . these product also may contain 3rd party ips that may require users to have authorization from the respective ip holders to receive them. royalty for use of the 3rd party ips may also be payable by users. figure 44. 144-lead lqfp (st-144-3) seating plane 1.6 0 m ax 0.1 5 0.0 5 0. 08 max (lead coplanarity) 1. 45 1. 40 1. 35 0.2 7 0.2 2 0.1 7 typ 0.50 bsc typ (lead pi tch) detail a de t ai l a 0.75 0.60 typ 0.45 1 36 37 72 108 144 10 9 top view (pins down) 22 .0 0 bsc s q 20.00 bsc sq notes: 1. dimensions are in millimeters and comply with jedec standard ms-026-bfb-hd. 2. actual position of each lead is within 0.08 of its ideal position, when measured in the lateral direction. 3. center dimensions are nominal. 4. heatslug is coincident with bottom surface and does not protrude beyond it. pin 1 indi ca tor heatslug on bottom (note 4) dia 12 .71 13 .21 13 .71
rev. pra | page 52 of 54 | september 2004 adsp-21365/6 preliminary technical data table 45. adsp-21365 ordering guide part number 1, 2, 3 ambient temperature range adsp-21365skbczeng 0 to 70 333mhz 3m bit 4m bit 1.2/3.3 136 mini-bga pb-free adsp-21365skbc-eng 0 to 70 333mhz 3m bit 4m bit 1.2/3.3 136 mini-bga adsp-21365sksqzeng 0 to 70 333mhz 3m bit 4m bit 1.2/3.3 144 intChs lqfp pb-free adsp-21365sksq-eng 0 to 70 333mhz 3m bit 4m bit 1.2/3.3 144 intChs lqfp adsp-21365sbbczeng 4 C40 to 85 333mhz 3m bit 4m bit 1.2/3.3 136 mini-bga pb-free adsp-21365sbbc-eng 4 C40 to 85 333mhz 3m bit 4m bit 1.2/3.3 136 mini-bga ADSP-21365SBSQZENG 5 C40 to 85 333mhz 3m bit 4m bit 1.2/3.3 144 intChs lqfp pb-free adsp-21365sbsq-eng 5 C40 to 85 333mhz 3m bit 4m bit 1.2/3.3 144 intChs lqfp adsp-21365scsqzeng 5 C40 to 105 200mhz 3m bit 4m bit 1.0/3.3 144 intChs lqfp pb-free adsp-21365scsq-eng 5 C40 to 105 200mhz 3m bit 4m bit 1.0/3.3 144 intChs lqfp 1 z indicates lead free package. for more information about lead free package of ferings, please visit www.analog.com. 2 see thermal characteristics on page 44 for information on packag e thermal specifications. 3 see engineerCtoCengineer note tbd for further information. 4 pcb must have thermal vias. see thermal characteristics on page 44 . for more information see jedec standard jesd51-9. 5 heat slug must be soldered to the pcb. see thermal characteristics on page 44 . for more information see jedec standard jesd51-5. table 46. adsp-21366 ordering guide part number 1, 2, 3 ambient temperature range adsp-21366skbczeng 0 to 70 333mhz 3m bit 4m bit 1.2/3.3 136 mini-bga pb-free adsp-21366skbc-eng 0 to 70 333mhz 3m bit 4m bit 1.2/3.3 136 mini-bga adsp-21366sksqzeng 0 to 70 333mhz 3m bit 4m bit 1.2/3.3 144 intChs lqfp pb-free adsp-21366sksq-eng 0 to 70 333mhz 3m bit 4m bit 1.2/3.3 144 intChs lqfp adsp-21366sbbczeng 4 C40 to 85 333mhz 3m bit 4m bit 1.2/3.3 136 mini-bga pb-free adsp-21366sbbc-eng 4 C40 to 85 333mhz 3m bit 4m bit 1.2/3.3 136 mini-bga adsp-21366sbsqzeng 5 C40 to 85 333mhz 3m bit 4m bit 1.2/3.3 144 intChs lqfp pb-free adsp-21366sbsq-eng 5 C40 to 85 333mhz 3m bit 4m bit 1.2/3.3 144 intChs lqfp adsp-21366scsqzeng 5 C40 to 105 200mhz 3m bit 4m bit 1.0/3.3 144 intChs lqfp pb-free adsp-21366scsq-eng 5 C40 to 105 200mhz 3m bit 4m bit 1.0/3.3 144 intChs lqfp 1 z indicates lead free package. for more information about lead free package of ferings, please visit www.analog.com. 2 see thermal characteristics on page 44 for information on packag e thermal specifications. 3 see engineerCtoCengineer note tbd for further information. 4 pcb must have thermal vias. see thermal characteristics on page 44 . for more information see jedec standard jesd51-9. 5 heat slug must be soldered to the pcb. see thermal characteristics on page 44 . for more information see jedec standard jesd51-5.
adsp-21365/6 preliminary technical data rev. pra | page 53 of 54 | september 2004
rev. pra | page 54 of 54 | september 2004 adsp-21365/6 preliminary technical data ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners.

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